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3348j?seepr?8/06 features serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) ? data sheet describes mode 0 operation low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 5.5v) 20 mhz clock rate (5v) 8-byte page mode block write protection ? protect 1/4, 1/2, or entire array write protect ( wp ) pin and write disable instructions for both hardware and software data protection self-timed write cycle (5 ms max) high reliability ? endurance: one million write cycles ? data retention: 100 years automotive devices available 8-lead jedec pdip, 8-lead jedec soic, 8- lead ultra thin mini -map (mlp 2x3) and 8- lead tssop packages die sales: wafer form, waffle pack, bumped wafers description the AT25010A/020a/040a provides 1024/2048/4096 bits of serial electrically eras - able programmable read-onl y memory (eeprom) organized as 128/256/512 words of 8 bits each. the device is optimized for use in many industrial and commercial appli - cations where low-power and low-voltage operation are essential. the AT25010A/020a/040a is available in space saving 8-lead pdip, 8-lead jedec soic, 8-lead ultra thin mini-map (mlp 2x3) , and 8-lead tssop packages. the AT25010A/020a/040a is enabled through the chip select pin ( cs ) and accessed via a three-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no separate erase cycle is required before write. block write protection is enabled by programming the status register with one of four blocks of write protection. separate program enable and program disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts. the hold pin may be used to suspend any serial communication without resetting the serial sequence. table 1. pin configuration pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input spi serial eeprom 1k (128x8) 2k (256x8) 4k (512x8) AT25010A at25020a at25040a 1 2 3 4 8 7 6 5 c s s o wp gnd vcc hold s ck s i 1 2 3 4 8 7 6 5 vcc hold s ck s i c s s o wp gnd 1 2 3 4 8 7 6 5 cs so wp gnd vc c ho l sc k si 1 2 3 4 8 7 6 5 cs so wp gnd vc c ho l sc k si 8 -le a d pdip 8 -le a d s oic 8 -le a d t ss op 8 -le a d ultr a thin mini-map (mlp 2x 3 ) bottom view
absolute maximum ratings* operating temperature .................................... ? 40c to + 125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam - age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ....................................... ? 65c to + 150c voltage on any pin with respect to ground ....................................... ? 1.0v to + 7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma 2 AT25010A/020a/040a 3348j?seepr?8/06 figure 1. block diagram memory array 12 8 /256/512 x 8 s tat u s regi s ter data regi s ter mode decode logic clock generator output buffer addre ss decoder
table 2. pin capacitance (1) applicable over recommended operating range from t a = 25c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance ( cs , sck, si, wp , hold ) 6 pf v in = 0v 3 AT25010A/020a/040a 3348j?seepr?8/06 note: 1. this parameter is characterized and is not 100% tested. table 3. dc characteristics (1) i cc2 supply current 4.5 5.0 ma i cc3 supply current 2.0 3.0 ma 3.6v v cc 5.5v 1.8v v cc 3.6v note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v, (unless otherwise noted) symbol parameter test co ndition min typ max units v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 20 mhz, so = open, read 8.5 10.0 ma v cc = 5.0v at 10 mhz, so = open, read, write v cc = 5.0v at 1 mhz, so = open, read, write i sb1 standby current v cc = 1.8v, cs = v cc 0.1 0.5 a i sb2 standby current v cc = 2.7v, cs = v cc 0.2 1.0 a i sb3 standby current v cc = 5.0v, cs = v cc 2.0 3.5 a i il input leakage v in = 0v to v cc ? 3.0 a i ol output leakage v in = 0v to v cc , t ac = 0c to 70c ? 3.0 3.0 a v il (1) input low-voltage ? 0.6 v cc x 0.3 v v ih (1) input high-voltage v cc x 0.7 v cc + 0.5 v v ol1 output low-voltage i ol = 3.0 ma 0.4 v v oh1 output high-voltage i oh = ? 1.6 ma v cc ? 0.8 v v ol2 output low-voltage i ol = 0.15 ma 0.2 v v oh2 output high-voltage i oh = ? 100 a v cc ? 0.2 v
4 AT25010A/020a/040a 3348j?seepr?8/06 table 4. ac characteristics applicable over recommended operating range from t ai = 40 to +85c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units f sck sck clock frequency 4.5 5.5 2.7 5.5 1.8 5.5 0 0 0 20 10 5 mhz t ri input rise time 4.5 5.5 2.7 5.5 1.8 5.5 2 2 2 s t fi input fall time 4.5 5.5 2.7 5.5 1.8 5.5 2 2 2 s t wh sck high time 4.5 5.5 2.7 5.5 1.8 5.5 20 40 80 ns t wl sck low time 4.5 5.5 2.7 5.5 1.8 5.5 20 40 80 ns t cs cs high time 4.5 5.5 2.7 5.5 1.8 5.5 100 100 200 ns t css cs setup time 4.5 5.5 2.7 5.5 1.8 5.5 100 100 200 ns t csh cs hold time 4.5 5.5 2.7 5.5 1.8 5.5 100 100 200 ns t su data in setup time 4.5 5.5 2.7 5.5 1.8 5.5 20 40 80 ns t h data in hold time 4.5 5.5 2.7 - 5.5 1.8 - 5.5 20 40 80 ns t hd hold setup time 4.5 5.5 2.7 5.5 1.8 5.5 20 40 80 ns t cd hold hold time 4.5 5.5 2.7 5.5 1.8 5.5 20 40 80 ns t v output valid 4.5 5.5 2.7 5.5 1.8 5.5 0 0 0 20 40 80 ns t ho output hold time 4.5 5.5 2.7 5.5 1.8 5.5 0 0 0 ns
5 AT25010A/020a/040a 3348j?seepr?8/06 note: 1. this parameter is characterized and is not 100% tested. t lz hold to output low z 4.5 5.5 2.7 5.5 1.8 5.5 0 0 0 25 50 100 ns t hz hold to output high z 4.5 5.5 2.7 5.5 1.8 5.5 25 50 100 ns t dis output disable time 4.5 5.5 2.7 5.5 1.8 5.5 25 50 100 ns t wc write cycle time 4.5 5.5 2.7 5.5 1.8 5.5 5 5 5 ms endurance (1) 5.0v, 25 q c, page mode 1m write cycles table 4. ac characteristics (continued) applicable over recommended operating range from t ai = 40 to +85c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units
6 AT25010A/020a/040a 3348j?seepr?8/06 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the AT25010A/020a/040a always operates as a slave. transmitter/receiver: the AT25010A/020a/040a has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. the op-code also contains address bit a8 in both the read and write instructions. invalid op-code: if an invalid op-code is received, no data will be shifted into the AT25010A/020a/040a, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the AT25010A/020a/040a is selected when the cs pin is low. when the device is not selected, da ta will not be accepted via the si pin, and the so pin will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the AT25010A/020a/040a. when the device is sele cted and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low, all write operations are inhibited. wp going low while cs is still low will interrupt a writ e to the AT25010A/020a/040a. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation.
7 AT25010A/020a/040a 3348j?seepr?8/06 figure 2. spi serial interface AT25010A/020a/040a
8 AT25010A/020a/040a 3348j?seepr?8/06 functional description table 5. instruction set for the AT25010A/020a/040a wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 a011 read data from memory array write 0000 a010 write data to memory array the AT25010A/020a/040a is designed to interfac e directly with the synchronous serial peripheral interface (spi) of the 6805 and 68hc11 series of microcontrollers. the AT25010A/020a/040a utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in figure 5. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. note: ?a? represents msb address bit a8. table 6. status register format x x x x bp1 bp0 wen rdy write enable (wren): the device will power up in the write disable state when v cc is applied. all programming instructions must therefore be preceded by a write enable instruction. the wp pin must be held high during a wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is indepen- dent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the read/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bi ts are set by using the wrsr instruction. write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the AT25010A/020a/040a is divided into four array seg- ments. one-quarter, one-half, or all of the memory segments can be protected. any of instruction name instru ction format operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 7. read status register bit definition bit definition bit 0 (rdy ) bit 0 = ?0? (rdy ) indicates the device is ready. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit 1 = ?0? indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table 8. bit 3 (bp1) see table 8. bits 4?7 are ?0?s when device is not in an internal write cycle. bits 0?7 are ?1?s during an internal write cycle.
9 AT25010A/020a/040a 3348j?seepr?8/06 the data within any selected segment will ther efore be read only. the block write protec- tion levels and corresponding status register control bits are shown in table 8. bits bp1 and bp0 are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., wren, t wc , rdsr). read sequence (read): reading the AT25010A/020a/040a via the so pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code (including a8) is transmitted vi a the si line followed by the byte address to be read (a7 a0). upon completion, any data on the si line will be ignored. the data (d7 d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is automatically incremented and data will continue to be shi fted out. when the highest addre ss is reached, the address counter will roll over to the lowest address a llowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the AT25010A/020a/040a, the write protect pin (wp ) must be held high and two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be pro- grammed must be outside the protected address field location selected by the block write protection level. duri ng an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code (including a8) is transmitted via the si line fol- lowed by the byte address (a7 a0) and the data (d7 d0) to be programmed. programming will start after the cs pin is brought high. the low-to-high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status reg- ister (rdsr) instruction. if bit 0 = ?1?, the write cycle is still in progress. if bit 0 = ?0?, the write cycle has ended. only the rdsr instruction is enabled during the write program- ming cycle. the AT25010A/020a/040a is capable of an 8-byte page write operation. after each byte of data is received, the three low-order address bits are internally incremented by one; the six high-order bits of the address will remain constant. if more than 8 bytes of data are transmitted, the address co unter will roll over and the prev iously written data will be overwritten. the AT25010A/020a/040a is automatically returned to the write disable state at the completion of a write cycle. note: if the wp pin is brought low or if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to reinitiate the serial communication. table 8. block write protect bits level status register bits array addresses protected bp1 bp0 AT25010A at25020a at25040a 0 0 0 none none none 1 (1/4) 0 1 60 7f c0 ff 180 ff 2 (1/2) 1 0 40 7f 80 ff 100 1ff 3 (all) 1 1 00 7f 00 ff 000 1ff
10 AT25010A/020a/040a 3348j?seepr?8/06 timing diagrams figure 3. synchronous data timing (for mode 0) s o v oh v ol hi-z hi-z t v valid in s i v ih v il t h t s u t di s s ck v ih v il t wh t c s h c s v ih v il t c ss t c s t wl t ho figure 4. wren timing figure 5. wrdi timing
11 AT25010A/020a/040a 3348j?seepr?8/06 figure 6. rdsr timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance 15 figure 7. wrsr timing c s s ck 012 3 4567 8 9 1011121 3 14 s i in s truction s o 7654 3 210 data in high impedance 15 figure 8. read timing
12 AT25010A/020a/040a 3348j?seepr?8/06 figure 9. write timing c s s ck 012 3 4567 8 9 1011121 3 14 s i in s truction s o 7654 3 210 data in high impedance 15 16 17 1 8 19 20 21 22 8 0 1 2 3 4 5 6 7 9th bit of addre ss 2 3 byte addre ss figure 10. hold timing s o s ck hold t cd t hd t hz t lz t cd t hd c s
AT25010A ordering information (1) AT25010A-10pu-2.7 (2) AT25010A-10pu-1.8 (2) AT25010An-10su-2.7 (2) AT25010An-10su-1.8 (2) AT25010A-10tu-2.7 (2) AT25010A-10tu-1.8 (2) AT25010Ay1-10yu-1.8 (2) (not recommended for new designs) AT25010Ay6-10yh-1.8 (3) 8p3 8p3 8s1 8s1 8a2 8a2 8y1 8y6 lead-free/halogen-free/ industrial temperature ( ? 40 to 85 c) AT25010A-w1.8-11 (4) die sale industrial temperature ( ? 40 to 85 c) 13 AT25010A/020a/040a 3348j?seepr?8/06 notes: 1. for 2.7v devices used in the 4.5 to 5.5v range, please refer to performance values in table on page 3 and table 4 on p age 4. 2. ?u? designates green package + rohs compliant. 3. ?h? designates green package + rohs compliant, with nipdau lead finish. 4. available in waffle pack and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact serial eeprom marketing. ordering code package operation range package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footpr int, non-leaded, miniature array package (map) 8y6 8-lead, 2.00mm x 3.00mm body, 0.50 mm pitch, ultra th in mini-map, dual no lead package (dfn), (mlp 2x3 mm) options ? 2.7 low voltage (2.7 to 5.5v) ? 1.8 low voltage (1.8 to 5.5v)
14 AT25010A/020a/040a 3348j?seepr?8/06 notes: 1. for 2.7v devices used in the 4.5 to 5.5v range, please refer to performance values in table on page 3 and table 4 on p age 4. 2. ?u? designates green package + rohs compliant. 3. ?h? designates green package + rohs compliant, with nipdau lead finish. 4. available in waffle pack and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact serial eeprom marketing. at25020a ordering information (1) ordering code package operation range at25020a-10pu-2.7 (2) at25020a-10pu-1.8 (2) at25020an-10su-2.7 (2) at25020an-10su-1.8 (2) at25020a-10tu-2.7 (2) at25020a-10tu-1.8 (2) at25020ay1-10yu-1.8 (2) (not recommended for new designs) at25020ay6-10yh-1.8 (3) 8p3 8p3 8s1 8s1 8a2 8a2 8y1 8y6 lead-free/halogen-free/ industrial temperature ( 40 to 85 q c) at25020a-w1.8-11 (4) die sale industrial temperature ( 40 to 85 q c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footpr int, non-leaded, miniature array package (map) 8y6 8-lead, 2.00mm x 3.00mm body, 0.50 mm pitch, ultra th in mini-map, dual no lead package (dfn), (mlp 2x3 mm) options 2.7 low voltage (2.7 to 5.5v) 1.8 low voltage (1.8 to 5.5v)
15 AT25010A/020a/040a 3348j?seepr?8/06 notes: 1. for 2.7v devices used in the 4.5 to 5.5v range, please refer to performance values in table on page 3 and table 4 on p age 4. 2. ?u? designates green package + rohs compliant. 3. ?h? designates green package + rohs compliant, with nipdau lead finish. 4. available in waffle pack and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact serial eeprom marketing. at25040a ordering information ordering code package operation range at25040a-10pu-2.7 (2) at25040a-10pu-1.8 (2) at25040an-10su-2.7 (2) at25040an-10su-1.8 (2) at25040a-10tu-2.7 (2) at25040a-10tu-1.8 (2) at25040ay1-10yu-1.8 (2) (not recommended for new designs) at25040ay6-10yh-1.8 (3) 8p3 8p3 8s1 8s1 8a2 8a2 8y1 8y6 lead-free/halogen-free/ industrial temperature ( 40 to 85 q c) at25040a-w1.8-11 (4) die sale industrial temperature ( 40 to 85 q c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footpr int, non-leaded, miniature array package (map) 8y6 8-lead, 2.00mm x 3.00mm body, 0.50 mm pitch, ultra th in mini-map, dual no lead package (dfn), (mlp 2x3 mm) options 2.7 low voltage (2.7 to 5.5v) 1.8 low voltage (1.8 to 5.5v)
16 AT25010A/020a/040a 3348j?seepr?8/06 packaging information 8p3 ? 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view pdip
17 AT25010A/020a/040a 3348j?seepr?8/06 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. note: 10/7/0 3 8s 1 , 8 -le a d (0.150" wide body), pl as tic g u ll wing s m a ll o u tline (jedec s oic) 8s 1b common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a1 0.10 ? 0.25 the s e dr a wing s a re for gener a l inform a tion only. refer to jedec dr a wing m s -012, v a ri a tion aa for proper dimen s ion s , toler a nce s , d a t u m s , etc. a1. 3 5 ? 1.75 b 0. 3 1 ? 0.51 c 0.17 ? 0.25 d4. 8 0 ? 5.00 e1 3 . 8 1? 3 .99 e 5.79 ? 6.20 e 1.27 b s c l 0.40 ? 1.27 ? 0? ? 8 ? ? top view end view s ide view e b d a a1 n e 1 c e1 l
18 AT25010A/020a/040a 3348j?seepr?8/06 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
19 AT25010A/020a/040a 3348j?seepr?8/06 8y1 ? map a ? ? 0.90 a1 0.00 ? 0.05 d 4.70 4.90 5.10 e 2. 8 0 3 .00 3 .20 d1 0. 8 5 1.00 1.15 e1 0. 8 5 1.00 1.15 b 0.25 0. 3 0 0. 3 5 e 0.65 typ l 0.50 0.60 0.70 pin 1 index area d e a a1 b 8 7 6 e 5 l d1 e1 pin 1 index area 1 2 3 4 a top view end view bottom view s ide view 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 y1, 8 -le a d (4.90 x 3 .00 mm body) m s op arr a y p a ck a ge (map) y1 c 8 y1 2/2 8 /0 3 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note
20 AT25010A/020a/040a 3348j?seepr?8/06 8y6 - mini-map 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y6 , 8-lead 2.0 x 3.0 mm body, 0.50 mm pitch, utlra thin mini-map, dual no lead package (dfn) ,(mlp 2x3) c 8y6 8/26/05 notes: 1. this drawing is for general information only. refer to jedec drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 - - 1.40 a - - 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 a3 0.20 ref l 0.20 0.30 0.40 e 0.50 bsc b 0.20 0.25 0.30 2 a2 b (8x) pin 1 id pin 1 index area a1 a3 d e a l (8x) e (6x) 1.50 ref. d2 e2
21 AT25010A/020a/040a 3348j?seepr?8/06 revision history doc. rev. comments 3348j revision history implemented; added ordering codes for at25020a and at25040a.
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